1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a high performance strained silicon, Fin field effect transistor (FinFET) device.
2. Description of the Related Art
Fin FETs are considered promising candidates for complementary metal oxide semiconductor (CMOS) device scaling (e.g., see Hu Chenming et al., U.S. Pat. No. 6,413,802 entitled “FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture”).
Indeed, FinFETs are a type of double gate structure which offer high silicon current delivery than single gate devices. Further, FinFETs improve the short channel characteristics of the device and are easier to scale down from.
The fabrication of a FinFET is generally simpler than most other double-gate structures, although the channel thickness control is problematic in most known approaches (e.g., see U.S. Pat. No. 6,413,802; Yang-Kyu Choi et al., “Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era”, Solid-State Electronics, 46, p. 1595, (2002)).
Additionally, to increase the device current drive, high carrier mobility is required. MOSFETs with high carrier mobility are made by fabricating the device on strained silicon (e.g., see K. Rim et al. “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's”, IEEE Trans. Electron Devices, 47(7), p. 1406, (2000)). A MOSFET fabricated in 001-oriented silicon under biaxial tensile strain exhibits higher carrier mobilities than a conventional MOSFET (e.g., see K. Rim, J. L. Hoyt, J. F. Gibbons, “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's”, IEEE Trans. Electron Devices, 47(7), p. 1406, (2000)). The higher carrier mobility leads to a higher current drive and thus a faster/shorter switching time is obtained.
The “strained” silicon film is typically formed by growing an epitaxial silicon layer on top of a strain-relaxed, graded SiGe layer structure (e.g., see P. M. Mooney, Materials Science and Engineering Reports R17, p. 105 (1996) and references therein).
As known, Ge has a lattice constant which is approximately 4% larger than the lattice constant of Si, and the lattice constant of the alloy, Si1-xGex, increases approximately linearly with increasing Ge mole fraction, x, of the alloy. Since these semiconductors have cubic symmetry, the in-plane and out-of-plane lattice constants are equal in unstrained crystalline films or bulk crystals.
Herein, “strained” (or fully strained) means that the in-plane lattice constant of the SiGe layer, which is larger than that of the Si substrate, is compressed so that it matches that of the Si substrate, thereby resulting in a corresponding expansion of the out-of-plane lattice parameter such that the in-plane and out-of-plane lattice parameters of the SiGe layer are no longer equal. A SiGe layer is partially strained or partially relaxed when the in-plane lattice parameter is larger than that of Si, but still smaller than the out-of-plane SiGe lattice parameter. The SiGe is fully “relaxed” or unstrained when the in-plane and out-of-plane lattice parameters are equal. For Si under biaxial tensile strain (e.g., when it is grown epitaxially on a partially or fully relaxed SiGe layer), the in-plane lattice parameter is larger than the out-of-plane lattice parameter.
Thus, strained silicon is useful for increasing the performance over conventional silicon devices. Indeed, a strained silicon (e.g., tensilely strained or compressively strained) may offer 1.5 times the carrier mobility over conventional silicon devices.
The conventional techniques for making strained silicon are applicable for planar devices such as the conventional MOSFET. Examples for such techniques are a graded buffer SiGe layer (e.g., see P. M. Mooney, Materials Science and Engineering Reports R17, p. 105 (1996) and references cited therein), and the relaxation by ion implantation and anneal (e.g., see U.S. Pat. No. 6,593,625 by S. H. Christiansen et al., entitled “Relaxed SiGe layers on Si or silicon on insulator substrates by ion implantation and thermal annealing”).
Thus, strained Si complementary metal oxide semiconductor (CMOS) devices with strained Si channel on a relaxed Si1-xGex buffer layer are known to offer better device performance over conventional Si CMOS because of the enhancement in both channel electron and hole mobilities in the strained silicon film.
That is, a MOSFET fabricated in 001-oriented silicon under biaxial tensile strain exhibits higher carrier mobilities than a conventional MOSFET (e.g., see K. Rim, J. L. Hoyt, J. F. Gibbons, “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's”, IEEE Trans. Electron Devices, 47(7), p. 1406, (2000)). The higher carrier mobility leads to a higher current drive and thus a faster/shorter switching time is obtained.
The “strained” silicon film is typically formed by growing an epitaxial silicon layer on top of a strain-relaxed, graded SiGe layer structure (e.g., see P. M. Mooney, Materials Science and Engineering Reports R17, p. 105 (1996) and references therein).
A thin SiGe layer grown epitaxially on a Si(001) substrate will be strained, with the in-plane lattice parameter matching that of the Si substrate. In contrast, when a thicker layer is grown, the strain will be relaxed by the introduction of dislocations, specifically 60° misfit dislocations when the lattice mismatch is <2%. The thicker the layer, the more dislocations present and the more relaxed the SiGe layer is. The misfit dislocation is the boundary of a missing plane of atoms. It is typically a half loop, with a misfit segment running parallel to the SiGe/Si interface terminating in threading arms that go the wafer surface. The presence of the misfit dislocation creates an atomic step at the wafer surface. Strain relaxation by the introduction of crystal defects is known as “plastic strain relaxation”.
Plastic strain relaxation results in a rough surface that exhibits a cross hatch pattern, which raises surface roughness/topography issues as described below, and a threading dislocation density in the range of 105-108 cm−2 in the upper part of the relaxed SiGe layer and the strained Si film. The strain fields from the misfit dislocation network introduce so-called mosaic structure in the SiGe and Si layers, which is detected as a broadening of the x-ray rocking curve. Triple-axis x-ray diffraction measurements can distinguish mosaic broadening from other effects, such as a non-uniform SiGe lattice parameter or alloy composition, that can also cause a broadening of the x-ray rocking curve. The exact nature of the mosaic structure in the upper part of the SiGe film and the strained Si layer is determined by the arrangement of the misfit dislocations, which will vary depending on the SiGe layer structure and the epitaxial growth conditions used to fabricate the structure.
Thus, such strained silicon channels improve and increase the silicon current delivery capability, and improve the short channel characteristics. Additionally, such strained silicon devices are easier to scale down from. Further, strained silicon is used to increase performance by making the channel strained (tensile), an increase of 1.5 times the mobility of conventional silicon can be achieved.
However, such strained silicon channels have not been demonstrated for devices as small as 50 nm or less.
As mentioned above, another conventional device is the FinFET, which has found advantageous use because of its double gate structure. That is, conventional devices have typically used a single gate structure. The FinFET uses a double gate structure, thereby to allow more control and to reduce power.
However, for FinFET devices, strained silicon has been difficult to integrate due to the geometry of the fin and the gate and the fabrication process.
Thus, prior to the present invention, there has been no effective method (nor structure resulting from the method), in which FinFET devices have been formed with strained silicon. Such a combination of strained silicon with a silicon FinFET would offer enhanced channel mobility and be substantially defect-free.